The present invention relates generally to integrated circuits and in particular the present invention relates to non-volatile memory devices with elevated program/erase voltage levels.
The use of non-volatile memory systems that maintain data integrity when a power supply is removed are expanding rapidly in integrated circuit technology. A class of non-volatile memory systems having memory cells which have a source, a drain, a channel, a floating gate over the channel and a control gate are widely used. Two popular types of non-volatile memory designs in this class are electronically erasable and programmable read only memories (EEPROM) and FLASH erasable-programmable read only memory (EPROM). The FLASH EPROM or flash memory system allows the simultaneous erasure of multiple memory cells.
The floating gate of the memory cell stores data and are generally formed from polysilicon members completely surrounded by an insulator. A flash memory cell is programmed when a charge is stored on the floating gate. Moreover, a memory cell is un-programmed, or erased, when the charge is removed from the floating gate.
One method of programning a memory cell is accomplished by applying a positive potential (e.g., 4-7 V) to its drain and a programming potential (e.g., 10-15) to its control gate. This causes electrons to be transferred from the source to the floating gate of the memory cell. One method of erasing a memory cell is accomplished by applying a positive potential (e.g., 10-15 V) to its source while grounding the control gate and letting the drain float. This action removes electrons from the floating gate. The programming action of transferring electrons to the floating gate results in a memory cell that conducts less current when read than it would otherwise in the un-programmed state.
The flash memory may also include a charge pump or similar circuit that generates an elevated voltage, Vpp, used during programming of the memory cells and other internal operations. During write operations, Vpp is coupled to the memory cells for providing appropriate write operation programming power. Charge pump designs are known to those skilled in the art, and provides power which is dependant upon an externally provided supply of voltage Vcc.
The source of elevated programming voltage in a non-volatile memory should be discharged after a write or erase action takes place. This is typically accomplished by disabling the charge pump or other source of power and discharging the remaining charge in the source to ground. The spike of current that happens as this discharge occurs is a common source of noise in systems containing non-volatile memory devices, in particular for modern non-volatile memory systems with multiple independent sections. This noise needs to be addressed and reduced to avoid potential faults in the system and circuitry.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to reduce discharge noise from programming voltage power sources in non-volatile memories and systems containing non-volatile memories.
The above-mentioned problems with memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises a charge pump to provide an output voltage, and a discharge circuit coupled to discharge the output voltage of the charge pump. The discharge circuit has a controllable discharge current path to control a discharge time of the output voltage.
In another embodiment, a memory device comprises a charge pump to provide an output voltage on an output connection, and a discharge circuit coupled to the output connection of the charge pump. The discharge circuit comprises a discharge transistor coupled between the output connection of the charge pump and a discharge voltage connection, and a control transistor coupled between the output connection and a gate of the discharge transistor. The control transistor is selectively activated during operation of the charge pump. A capacitor is coupled to the gate of the discharge transistor. The capacitor is charged by the charge pump output voltage during the operation of the charge pump. A control circuit is provided with output node coupled to regulate a gate voltage of the discharge transistor such that the discharge transistor is operated in a linear region to control the discharge time of the output voltage. Finally, an isolation transistor is coupled between the gate of the discharge transistor and the control circuit.
In yet another embodiment, flash memory device comprises an array of non-volatile memory cells, a charge pump to provide a negative output voltage on an output node, control circuitry to control data states of the memory cells using the negative output voltage, and a discharge circuit coupled to the output node of the charge pump to discharge the negative voltage using a discharge transistor operated in a linear region to regulate a discharge current conducted by the discharge transistor.
A method of operating a memory device is provided that comprises generating a charge pump voltage on a charge pump output, and discharging the charge pump voltage using a regulated discharge circuit. The regulated discharge circuit provides an adjustable discharge time period.
Another method of operating a memory device is provided that comprises generating a negative charge pump voltage on a charge pump output when the charge pump is in an active mode, and charging a transistor to the negative charge pump voltage. The capacitor is coupled to a gate of an n-channel discharge transistor that is coupled to the charge pump output. The method further comprises providing a constant charging current to the capacitor when the charge pump is not in the active mode, such that a voltage of the capacitor is ramped from the negative charge pump voltage to a positive voltage to control a discharge current through the n-channel discharge transistor.